1. Field of the Invention
This invention relates to converter circuits such as digital-to-analog converters (DACs), and more particularly to converters with a resistance element that compensates for voltage drops across the switches of the device""s decrementing resistance network.
2. Description of the Related Art
A conventional DAC employing an R-2R decrementing resistor ladder is illustrated in FIG. 1. A number of equal value resistors having a common unit resistance R are connected in series with a voltage supply Vref, with rungs of the ladder tapped off the series circuit and having common resistance values equal to 2R, along with a terminal resistor of value 2R shown at the right end of the ladder. Each 2R resistor is connected to a respective bit switch S1, S2, S3 . . . Sn for the first, second, third and nth bits of the DAC, with the terminal 2R resistor connected through a terminal switch St that is always ON. Each bit switch includes one pole that is grounded and active when the switch is OFF to divert the bit current to ground, and an output pole that is active when the switch is ON and connected to the output poles from each of the other switches to yield an accumulated output current Iout that represents the total currents flowing through each of the ON switches at any given time. The termination switch St is always connected to ground. In the example illustrated in FIG. 1, the switches S1, S3 and Sn for the most significant, third most significant and least significant bits, respectively, are illustrated as being ON, while the switch S2 for the second most significant bit is illustrated as being OFF, along with St. Iout is therefore equal to the sum of the currents flowing through S1, S3, Sn and any other bit switches that may be ON. The circuit as described thus far is well known, and is discussed for example in Cecil, xe2x80x9cA CMOS 10-Bit D/A Converterxe2x80x9d, IEEE International Solid State Circuits Conf., February 1974, pp. 196-197.
A conventional control circuit for the ladder switches is illustrated in FIG. 2, in which digital signals from a digital input 2 are applied to a decoder 4 that decodes the digital input into control signals for the various ladder switches. Only the first bit switch S1 is shown in detail, but the other bit switches S2, S3 . . . Sn are similar in design. In this example, the ladder switches are implemented by respective pairs of NMOS transistors N1 and N2, with the source of each transistor connected in common to the 2R resistor for that bit, the drain of N1 grounded, and the drain of N2 connected to contribute to Iout. Other types of FETs or bipolar transistors could also be used for the switches. The decoder 4 supplies control signals to the gates of N1 and N2, holding N1 ON and N2 OFF when the overall switch S1 is to be OFF, and holding N1 OFF and N2 ON when the overall switch S1 is to be ON. Similar pairs of control signals are supplied from the decoder to the transistor pairs of the other ladder switches.
Returning to FIG. 1, Iout is supplied to an output amplifier A1, preferably an operational amplifier (op amp) with its inverting input receiving Iout and its non-inverting input grounded. A feedback circuit is connected between the output and inverting input of op amp A1, with an effective feedback resistance Rfb typically having a resistance value equal to R. For more recent DACs with a larger number of bits than the 10 bit DAC described in the Cecil article mentioned above, a compensation resistance element Rsw has been added in series with Rfb to compensate for an error that appears in the full scale DAC output because of voltage drops across the bit switches. While this is not a particular problem for lower resolution DACs such as the 10 bit device discussed in the Cecil article, it does introduce a noticeable error for higher resolution devices such as present 16 bit DACs. When all the bit switches are ON, the output voltage is offset from the desired full scale value by the voltage across the least significant bit. To compensate for this, the compensation resistance element Rsw has been implemented as a dummy switch which is continuously ON when the op amp is operating, and has a resistance equal to half the resistance of the most significant bit switch S1. A CMOS device such as the NMOS switches employed in FIG. 1 basically functions as a small resistor for this purpose, with an ON resistance value that can be controlled by the device geometry and is also a function of the voltage supply Vref. Therefore, the compensation resistance element Rsw has been implemented as an NMOS transistor that is always ON and has an ON resistance equal to half the S1 resistance.
Previous DACs exhibited an additional error due to the fact that the resistors in the resistance ladder were characterized by a temperature coefficient of resistance (TCR) that was significantly lower than the TCR of the ON NMOS resistance, typically on the order of 50 ppm/xc2x0 C. for the resistors vs. 4,000 ppm/xc2x0 C. for the transistors. This introduced an additional error over an operating temperature range. Implementing Rfb with true resistor elements and Rsw with an NMOS transistor compensated for this TCR differential, in addition to compensating for the bit switch voltage drops.
While the resistance Rfb may be considered as a single effective resistance value for most purposes, in practice it has generally been implemented as a network of series and parallel individual resistor elements to spread the associated heat loss.
The dummy feedback switch Rsw is useful for the compensation purposes discussed above, but it introduces some problems of its own. To obtain a resistance value half that of S1, it has been implemented with a width twice that of S1. This makes Rsw quite large, which not only wastes die area, but also adds a degree of unwanted capacitance that can slow down the operation of the circuit and ultimately destabilize the op amp.
The present invention seeks to provide a DAC and associated amplifier with a feedback circuit that achieves a compensation equivalent to that of the prior art, but requires significantly less area and gains a corresponding reduction in parasitic capacitance.
These goals are achieved by providing a feedback circuit for the DAC""s output amplifier that includes a compensation resistance element having a TCR within the range of the DAC bit switches, and connected in a combined series/parallel circuit with a feedback resistance circuit having a TCR within the range of the DAC ladder resistors. The resulting feedback circuit has an effective resistance approximately equal to the desired feedback resistance Rfb with a TCR within the ladder resistor TCR range, and an effective resistance with a TCR within the bit switch TCR range to at least approximately compensate for voltage drops across the switches.
In one embodiment of the invention, the feedback circuit for the DAC output amplifier includes a continuously ON compensation switch similar to the bit switches and having a resistance approximately equal to four times the resistance, and therefore approximately xc2xc the area, of the resistance for the most significant bit switch. The feedback circuit further includes a first feedback resistance unit that is connected in a series circuit with the compensation switch, and a second feedback resistance unit that is connected in parallel with the series circuit, with the first and second feedback resistance units each having a resistance approximately equal to twice Rfb.
In a preferred implementation, the first and second feedback resistance units have similar layouts and are each smaller in size than a resistance circuit with a similar layout that would produce a resistance of Rfb; each feedback resistance unit can have an effective resistance of 2Rfb.
The compensation resistance element also preferably has a resistance substantially smaller than that of the first and second feedback resistance units, and can be implemented with an NMOS transistor that is continuously biased ON.